Job Responsibility：

1. Responsible for communicating and cooperating with circuit engineers to complete layout design;

2. Conduct DRC, DFM, LVS and ERC checks on layout design;

3. Familiar with layout design rules to avoid ESD, latch effect and other parasitic effects;

4. Assist the designer to complete the simulation;

5. Complete the preparation and archiving of design documents at each stage.

Job Requirements：

1. Bachelor degree or above in microelectronics, electronics or related major, 3 years or above analog circuit layout design

experience;

2. Familiar with CMOS semiconductor process and layout design and layout design process, in-depth understanding of noise

isolation, matching, parasitization and other factors;

3. Proficient in using Cadence layout design software and Calibre verification tools;

4. Strong sense of responsibility, good communication skills and team spirit.