Job Responsibility：

1. Design general IO circuit design, establish IO library of different processes;

2. ESD design experience, with actual mass production project experience (analog, mixed digital, high pressure, negative pressure, high ESD level experience is preferred);

3. Responsible for the chip ESD, Latch up, EFT and other protection capabilities to improve and optimize;

4. Guide layout engineer to complete layout design;

5. Cooperate to complete ESD/Latch-up/EFT testing of the product, conduct failure analysis and optimize the design scheme;

6. Write design reports, simulation reports, test reports and other related technical documents. 

Job Requirements：

1. Microelectronics, communication, electronic information and other related majors, have a solid semiconductor device and analog IC basic knowledge;

2. Bachelor's degree more than 5 years, master's degree more than 3 years analog circuit or IO circuit design experience;

3. Can skillfully build the ESD, EFT simulation model of the chip to predict the anti-interference level of the chip;

4. Have a solid analog circuit design theory, understanding IO system design and a variety of widely used IO standards;