Job Responsibility：

1. Make verification plan according to design specification;

2. Build verification platform and implement verification plan;

3. D on SV/UVM to build the chip system level and module level verification platform, and meet the coverage requirements;

4. Responsible for generating and maintaining design documents and reports related to verification process.

Job Requirements：

1. Bachelor degree or above in electronic engineering, major in microelectronics and integrated circuits, electronic information engineering, electronic science and technology;

2. 1-2 years of relevant work experience is preferred;

3. Familiar with IC design, verification process, independently complete verification related work, familiar with SoC verification is preferred;

4. Proficient in Verilog/Systemverilog, familiar with relevant EDA verification tools: NC-verilog, VCS, etc., or similar tools;

5. With a certain ing ability (such as Makefile, Perl,);

6. With C or C++ auxiliary verification ability is preferred;

7. Successful streaming experience is preferred;

8. Familiar with image, video algorithm is good;

9. With strong learning ability, independent problem-solving ability and good team spirit.