Job Responsibility：

1. Responsible for the development of SOC chip DFT program) including test SPEC, test plan, test structure definition;

2. Responsible for the implementation and verification of DFT circuits, including SCAN, MBIST, l0 Boundary Scan, ATPG and other testability circuit design;

3. Responsible for developing the test pattern with high coverage and low test cost;

4. Complete the timing constraints in DFT mode, and assist the PR team to complete DFT STA/Power signOff;

5. Cooperated with ATE test team to track chip test yield, assisted in analyzing and solving ATE test failure, and successfully realized chip mass production test;

6, Assist the front-end design team, complete the digital circuit DC, FM, STA, power analysis, etc.

Job Requirements：

1. Bachelor degree or above, microelectronics/electronic information/electronic engineering/computer related major;

2. With more than 3 years of DFT design experience, familiar with Verilog, Per, TCL and other design and ing languages and DFT tools of Mentor or Synopsys;

3. Familiar with comprehensive and static timing analysis process, tool use and writing;

4. Experience in chip flow mass production and ATE test failure analysis is preferred;

5. Strong communication skills, organization and coordination skills and team spirit:

6. Strong logical thinking ability, learning ability, innovation ability, analysis and problem-solving ability and ability to work under pressure.