Job Responsibility：

1. Participate in the verification of related problems, support the SoC design of chip projects;

2. Use System Verilog to build a practical and efficient system-level simulation verification environment; Extract verification points, execute

verification use cases, and complete verification of relevant verification points;

3. Develop verification plan according to project requirements, and create system-level test cases according to the verification plan to ensure the

functional correctness of ASIC;

4. Responsible for generating and maintaining design documents and reports related to verification process.

Job Requirements：

1. UVM working experience is preferred;

2. Familiar with Linux working environment, master bash, csh, perl, tcl and other ing languages; Master UVM/OVM/VMM verification methods;

3. Understand the digital IC design process, SOC product design experience is preferred;

4. Have a strong learning ability, analytical skills, communication skills, a good team spirit.