Job Responsibility：

1. Design general IO circuit design, establish IO library of different processes;

2. ESD design experience, with analog, digital-analog mixed, high pressure, negative pressure, high ESD level experience is preferred;

3. Responsible for the improvement and optimization of chip ESD, Latch up, EFT and other protection capabilities;

4. Cooperate with layout engineer to complete layout design;

5. Cooperate to complete ESD/Latch-up/EFT testing of the product, conduct failure analysis and optimize the design scheme;

6. Write design reports, simulation reports, test reports and other related technical documents.

Job Requirements：

1. Microelectronics related bachelor degree or above;

2. Microelectronics, communication, electronic information and other related majors, have a solid semiconductor device and analog IC basic knowledge;

3. Can build the ESD, EFT simulation model of the chip to predict the anti-interference level of the chip;

4. Have a solid analog circuit design theory, understanding IO system design and a variety of widely used IO standards;

5. Have a strong learning ability, analytical skills, communication skills, team spirit.